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nx2139a 1 rev. 2.3 03/19/09 typical application description the nx2139a controller ic is a compact buck control- ler ic with 16 lead mlpq package designed for step down dc to dc converter in portable applications. it can be selected to operate in synchronous mode or non-synchronous mode to improve the efficiency at light load.constant on time control provides fast response, good line regulation and nearly constant frequency un- der wide voltage input range. the nx2139a controller is optimized to convert single supply up to 24v bus voltage to as low as 0.75v output voltage. over cur- rent protection and fb uvlo followed by latch fea- ture. a built-in ldo controller can drive an external n- mosfet to provide a second output voltage from ei- ther pwm output source or other power source. both pwm controller and ldo controller have separate en feature. other features includes: 5v gate drive capa- bility, power good indicator, over voltage protection, internal boost schottky diode and adaptive dead band control. n internal boost schottky diode n ultrasonic mode operation available n bus voltage operation from 4.5v to 24v n less than 1ua shutdown current with enable low n excellent dynamic response with constant on time control n selectable between synchronous ccm mode and diode emulation mode to improve efficiency at light load n programmable switching frequency n current limit and fb uvlo with latch off n over voltage protection with latch off n ldo controller with seperate enable n two independent power good indicator available n pb-free and rohs compliant ordering information features single channel mobile pwm and ldo controller applications n notebook pcs and desknotes n tablet pcs/slates n on board dc to dc such as 12v to 3.3v, 2.5v or 1.8v n hand-held portable instruments preliminary data sheet figure1 - typical application of nx2139a device temperature package pb-free NX2139ACMTR -10 o c to 100 o c 3x3 mlpq-16l yes pb free product vin 7v~22v ton hdrv bst sw ldrv ocset fb vout ensw /mode 5v 10 vcc pvcc pgood vout 1.8v/7a gnd 1.5v@2a ldodrv ldofb enldo ldopg 5v ldopg pgood 1meg 4 9 2 15 14 5 pad 6 7 3 1 10 8 11 13 12 16 100k 1u 1u 100k 50 33n 20k 1n 7.5k 7.5k 7.5k 2x10uf 10.5k 2r5tpe330mc 5k 1u 2x10uf 1n irf7807 ao4714 1.5uh n x 2 1 3 9 a 330uf m3 si4800 330p 2.2
nx2139a 2 rev. 2.3 03/19/09 9 10 11 12 4 3 2 1 vcc ton fb pgood pvcc ocset sw hdrv 8 7 6 5 ldodrv ldrv ldopg ldofb 16 15 14 13 enldo vo ensw/mode bst agnd 17 absolute maximum ratings vcc,pvcc to gnd & bst to sw voltage ............ -0.3v to 6.5v ton to gnd ......................................................... -0.3v to 28v hdrv to sw voltage .......................................... -0.3v to 6.5v sw to gnd ......................................................... -2v to 30v all other pins ........................................................ vcc+0.3v storage temperature range ..................................-65 o c to 150 o c operating junction temperature range .................-40 o c to 150 o c esd susceptibility ............................................... 2kv caution: stresses above those listed in "absolute maximum ratings", may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. package information 3x3 16-lead plastic mlpq electrical specifications unless otherwise specified, these specifications apply over vcc =5v, vin=15v and t a =25 o c , unless otherwise specified. o ja cw q?46/ parameter sym test condition min typ max units vin recommended voltage range v in 4.5 24 v shut down current enldo=gnd, ensw=gnd 1 ua vcc,pvcc supply input voltage range v cc 4.5 5.5 v operating quiescent current vfb=0.85v, enldo=gnd, ensw=5v 1.8 ma shut down current enldo=gnd, ensw=gnd 1 ua
nx2139a 3 rev. 2.3 03/19/09 n parameter sym test condition min typ max units vcc uvlo under-voltage lockout threshold v cc _uvlo 3.9 4.1 4.5 v falling vcc threshold 3.7 3.9 4.3 v on and off time ton operating current vin=15v, rton=1mohm 15 ua on -time vin=9v,vout=0.75v, rton=1mohm 312 390 468 ns minimum off time 380 590 800 ns fb voltage internal fb voltage vref 0.739 0.75 0.761 v input bias current 100 na line regulation vcc from 4.5v to 5.5v -1 1 % output voltage output range 0.75 3.3 v vout shut down discharge resistance ensw/mode=gnd 30 ohm soft start time 1.5 ms pgood pgood high rising threshold 90 % vref pgood delay after softstart note1 1.6 ms pgood propagation delay filter note1 2 us power good hysteresis 5 % pgood output switch impedance 13 ohm pgood leakage current 1 ua sw zero cross comparator offset voltage 5 mv high side driver (cl=3300pf) output impedance , sourcing current r source (hdrv) i=200ma 1.5 ohm output impedance , sinking current r sink (hdrv) i=200ma 1.5 ohm rise time thdrv(rise) 10% to 90% 50 ns fall time thdrv(fall) 90% to 10% 50 ns deadband time tdead(l to h) ldrv going low to hdrv going high, 10% to 10% 30 ns low side driver (cl=3300pf) output impedance, sourcing current r source (ldrv) i=200ma 1.5 ohm output impedance, sinking current r sink (ldrv) i=200ma 0.5 ohm rise time tldrv(rise) 10% to 90% 50 ns fall time tldrv(fall) 90% to 10% 50 ns 10 ns deadband time tdead(h to l) sw going low to ldrv going high, 10% to 10%
nx2139a 4 rev. 2.3 03/19/09 note1: this parameter is guaranteed by design but not tested in production(gbnt). parameter sym test condition min typ max units ensw/mode threshold and bias current pfm/non synchronous mode 80% vcc vcc+0 .3v v ultrasonic mode 60% vcc 80% vcc v synchronous mode leave it open or use limits in spec 2 60% vcc v shutdown mode 0 0.8 v ensw/mode=vcc 5 ua ensw/mode=gnd -5 ua ldo controller quiescent current pwm off, ldoen=hi, iout=0ma 1 ma ldoen logic high voltage 2 v ldoen logic low voltage 0.8 v ldofb reference voltage 0.728 0.75 0.773 v output uvlo threshold 70 %vref open loop gain note1 60 db ldofb input bias current 1 ua ldodrv sourcing current ldofb=0.72v 2 ma ldodrv sinking current ldofb=0.78v 2 ma ldo pgood threshold 90 %vref ldo pgood propagation delay filter note1 2 us ldo pgood impedance 13 ohm current limit ocset setting current 20 24 28 ua over temperature threshold note1 155 o c hysteresis 15 o c under voltage fb threshold 70 %vref over voltage over voltage tripp point 125 %vref internal schottky diode forward voltage drop forward current=50ma 500 mv input bias current
nx2139a 5 rev. 2.3 03/19/09 pin descriptions pin number pin symbol pin description this pin is directly connected to the output of the switching regulator and senses the vout voltage. an internal mosfet discharges the output during turn off. this pin supplies the internal 5v bias circuit. a 1uf x7r ceramic capacitor is placed as close as possible to this pin and ground pin. this pin is the error amplifiers inverting input. this pin is connected via resistor divider to the output of the switching regulator to set the output dc voltage from 0.75v to 3.3v. pgood indicator for switching regulator. it requires a pull up resistor to vcc or lower voltage. when fb pin reaches 90% of the reference voltage pgood transitions from lo to hi state. pgood indicator for ldo, requires a pull up resistor to vcc or lower volt- age. when ldofb pin reaches 90% of the reference voltage pgood transitions from lo to hi state. this pin is the error amplifiers inverting input. this pin is connected via resistor divider to the output of the ldo to set the output dc voltage. the drive signal for external ldo n channel mosfet. low side gate driver output. provide the voltage supply to the lower mosfet drivers. place a high frequency decoupling capacitor 1uf x5r to this pin. this pin is connected to the drain of the external low side mosfet and is the input of over current protection(ocp) comparator. an internal current source is flown to the external resistor which sets the ocp voltage across the rdson of the low side mosfet. this pin is connected to source of high side fets and provide return path for the high side driver. it is also the input of zero current sensing comparator. high side gate driver output. this pin supplies voltage to high side fet driver. a high freq 1uf x7r ceramic capacitor and 2.2ohm resistor in series are recommended to be placed as close as possible to and connected to this pin and sw pin. ldo enable input functions only when ensw/mode is not shutdown. switching converter enable input. connect to vcc for pfm/non synchronous mode, connected to an external resistor divider equals to 70%vcc for ultra- sonic, connected to gnd for shutdown mode, floating or connected to 2v for the synchronous mode. vin sensing input. a resistor connects from this pin to vin will set the fre- quency. a 1nf capacitor from this pin to gnd is recommended to ensure the proper operation. power ground. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pad vout vcc fb pgood ldopg ldofb ldodrv ldrv pvcc ocset sw hdrv bst enldo ensw/ mode ton gnd
nx2139a 6 rev. 2.3 03/19/09 block diagram figure 2 - simplified block diagram of the nx2139a soft start vin bst(13) hdrv(12) ldrv(8) pgnd sw(11) pvcc(9) 5v fet driver start odb hd_in start vout(1) 0.9*vref ss_finished pgood(4) ocset(10) ensw /mode(15) start por fb(3) gnd(17 pad) ton(16) hd vref=0.75v fbuvlo_latch r s q mini offtime 400ns ocp_comp hd diode emulation ocp_comp 0.7*vref fb 1.25*vref/0.7vref fb ovp fbuvlo_latch vout sync pfm_nonultrasonic 4.3/4.1 vcc(2) bias por disable disable_b 0.9*vref ldoss_finished ldopg(5) enldo(14) ldo_por ldodrv(7) ldofb(6) 0.7*vref ldofbuvlo_latch ldofbuvlo_latch vout vin 1.5v@2a~5a 1.8v thermal shutdown soft start on time pulse genearation vout mode selection ldo_en vcc 1m 1m
nx2139a 7 rev. 2.3 03/19/09 figure 3 - demo board schematic vin 7v~22v ton hdrv bst sw ldrv ocset fb vout ensw /mode 5v 10 vcc pvcc pgood vout 1.8v/7a gnd 1.5v@2a ldodrv ldofb enldo ldopg 5v ldopg pgood 1meg 4 9 2 15 14 5 pad 6 7 3 1 10 8 11 13 12 16 100k 1u 1u 100k 50 33n 20k 1n 7.5k 7.5k 7.5k co2 2x10uf 10.5k 2r5tpe330mc 5k 1u ci1 2x10uf 1n irf7807 ao4714 1.5uh n x 2 1 3 9 a 330uf r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 m1 m2 lo co1 c1 c2 c3 c5 c4 c6 2.2 1.5n r12 c7 m3 si4800 330p c8 2.2 r13 typical application (vin=7v to 22v, sw vout=1.8v/7a, ldo vout=1.5v/2a)
nx2139a 8 rev. 2.3 03/19/09 bill of materials item quantity reference value manufacture 1 2 ci1 10uf/25v/x5r 2 2 co2 10uf/6.3v/x5r 3 1 co1 2r5tpe330mc sanyo 4 3 c1,c2,c4 1uf 5 2 c3,c5 1nf 6 1 c6 33nf 7 1 c7 1.5nf 8 1 c8 330pf 9 1 lo do5010h-152 coilcraft 10 1 m1 irf7807 ir 11 1 m2 ao4714 aos 12 1 m3 si4800 philips 13 2 r1,r3 100k 14 1 r2 10 15 1 r4 1m 16 1 r5 5k 17 1 r6 10.5k 18 3 r7,r10,r11 7.5k 19 1 r8 50 20 1 r9 20k 21 2 r12,r13 2.2 22 1 u1 nx2139a nexsem inc.
nx2139a 9 rev. 2.3 03/19/09 fig.6 ldo output transient with sw in pfm mode (ch1 1.8v output ac, ch2 1.5v ldo ac, ch4 ldo output current) demoboard waveforms fig.4 startup (ch1 1.8v output, ch2 1.5v ldo, ch3 sw pgood, ch4 ldo pgood) fig.5 turn off (ch1 1.8v output, ch2 1.5v ldo, ch3 sw pgood, ch4 ldo pgood) fig. 9 vout ripple @ vin=12v,iout=4a (ch1 sw, ch3 vout ac) fig.7 sw output transient (ch1 1.8v output ac, ch2 1.5v ldo ac, ch4 1.8v output current) fig.8 start into short (ch1 vin, ch2 5v vcc, ch4 inductor current)
nx2139a 10 rev. 2.3 03/19/09 fig. 10 output efficiency vin=12v, vout=1.8v 50.00% 60.00% 70.00% 80.00% 90.00% 100.00% 10 100 1000 10000 output current(ma) output efficiency(%)
nx2139a 11 rev. 2.3 03/19/09 application information symbol used in application information: v in - input voltage v out - output voltage i out - output current d v ripple - output voltage ripple f s - working frequency d i ripple - inductor current ripple design example the following is typical application for nx2139a, the schematic is figure 1. v in = 7 to 22v v out =1.8v f s =220khz i out =7a d v ripple <=60mv d v droop <=60mv @ 3a step on_time and frequency calculation the constant on time control technique used in nx2139a delivers high efficiency, excellent transient dynamic response, make it a good candidate for step down notebook applications. an internal one shot timer turns on the high side driver with an on time which is proportional to the input supply v in as well inversely proportional to the output voltage v out . during this time, the output inductor charges the output cap increasing the output voltage by the amount equal to the output ripple. once the timer turns off, the hdrv turns off and cause the output voltage to decrease until reaching the internal fb volt- age of 0.75v on the pfm comparator. at this point the comparator trips causing the cycle to repeat itself. a minimum off time of 400ns is internally set. the equation setting the on time is as follows: 12 tonout in 4.4510rv ton v0.5v - = - ...(1) out s in v f vton = ...(2) in this application example, the rton is chosen to be 1mohm , when vin=22v, the ton is 372ns and f s is around 220khz. output inductor selection the value of inductor is decided by inductor ripple current and working frequency. larger inductor value normally means smaller ripple current. however if the inductance is chosen too large, it brings slow response and lower efficiency. the ripple current is a design free- dom which can be decided by design engineer accord- ing to various application requirements. the inductor value can be calculated by using the following equa- tions: ( ) inout on out ripple rippleoutput v-vt l= i i=ki ...(3) where k is percentage of output current. in this example, inductor from coilcraft do5010h-152 with l=1.5uh is chosen. current ripple is recalculated as below: inout on ripple out (v-v)t i= l (22v-1.8v)372ns = 1.5uh =5a ...(4) output capacitor selection output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(dc) load condition as well as specifica- tion for the load transient. the optimum design may require a couple of iterations to satisfy both conditions. based on dc load condition the amount of voltage ripple during the dc load condition is determined by equation(5). d d=d+ ripple rippleripple sout i vesri 8fc ...(5) where esr is the output capacitors' equivalent series resistance,c out is the value of output capaci- tors. typically poscap is recommended to use in nx2139's applications. the amount of the output volt- age ripple is dominated by the first term in equation(5)
nx2139a 12 rev. 2.3 03/19/09 and the second term can be neglected. for this example, one poscap 2r5tpe330mc is chosen as output capacitor, the esr and inductor current typically determines the output voltage ripple. when vin reach maximum voltage, the output volt- age ripple is in the worst case. ripple desire ripple v 60mv esr=12m i5a d ==w d ...(6) if low esr is required, for most applications, mul- tiple capacitors in parallel are needed. the number of output capacitor can be calculate as the following: eripple ripple esri n v d = d . ..(7) 12m5a n 60mv w = n =1 the number of capacitor has to be round up to a integer. choose n =1. based on transient requirement typically, the output voltage droop during tran- sient is specified as d v droop d v tran < @step load d i step during the transient, the voltage droop during the transient is composed of two sections. one section is dependent on the esr of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. for example, for the over- shoot when load from high load to light load with a di step transient load, if assuming the bandwidth of sys- tem is high enough, the overshoot can be estimated as the following equation. 2 out overshootstep out v vesri 2lc d=d+t ...(8) where t is the a function of capacitor,etc. crit step outcrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(9 where outouteeout crit stepstep esrcvesrcv l ii == dd ...(10) where esr e and c e represents esr and capaci- tance of each capacitor if multiple capacitors are used in parallel. the above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the esr of output capacitor. for low frequency ca- pacitor such as electrolytic capacitor, the product of esr and capacitance is high and crit ll is true. in that case, the transient spec is mostly like to depen- dent on the esr of capacitor. most case, the output capacitor is multiple ca- pacitor in parallel. the number of capacitor can be cal- culated by the following estep 2 out tranetran esri v n v2lcv d =+t dd ...(11) where crit step eecrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(12) for example, assume voltage droop during tran- sient is 60mv for 3a load step. if one poscap 2r5tpe330mc(330uf, 12mohm esr) is used, the crticial inductance is given as eeout crit step esrcv l i 12m3300f1.8v 23.76h 3a == d wm =m the selected inductor is 1.5uh which is smaller than critical inductance. in that case, the output volt- age transient mainly dependent on the esr. number of capacitor is estep tran esri n v 12m3a 60mv 0.6 d = d w = = choose n=1.
nx2139a 13 rev. 2.3 03/19/09 based on stability requirement esr of the output capacitor can not be chosen too low which will cause system unstable. the zero caused by output capacitor's esr must satisfy the re- quirement as below: sw esr out f 1 f 2esrc4 = p ...(13) besides that, esr has to be bigger enough so that the output voltage ripple can provide enough volt- age ramp to error amplifier through fb pin. if esr is too small, the error amplifier can not correctly dectect the ramp, high side mosfet will be only turned off for minimum time 400ns. double pulsing and bigger out- put ripple will be observed. in summary, the esr of output capacitor has to be big enough to make the sys- tem stable, but also has to be small enough to satify the transient and dc ripple requirements. input capacitor selection input capacitors are usually a mix of high fre- quency ceramic capacitors and bulk capacitors. ce- ramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the mosfets. usually 1uf ceramic capacitor is chosen to decouple the high frequency noise.the bulk input capacitors are decided by voltage rating and rms cur- rent rating. the rms current in the input capacitors can be calculated as: rmsout ons iid1-d dtf = = ...(14) when v in = 22v, v out =1.8v, i out =7a, the result of input rms current is 1.9a. for higher efficiency, low esr capacitors are recommended. one 10uf/x5r/25v and two 4.7uf/ x5r/25v ceramic capacitors are chosen as input capacitors. power mosfets selection the nx2139a requires at least two n-channel power mosfets. the selection of mosfets is based on maximum drain source voltage, gate source volt- age, maximum current rating, mosfet on resistance and power dissipation. the main consideration is the power loss contribution of mosfets to the overall con- verter efficiency. in this application, one irf7807 for high side and one ao4714 with integrated schottky di- ode for low side are used. there are two factors causing the mosfet power loss:conduction loss, switching loss. conduction loss is simply defined as: - + 2 hconoutds(on) 2 lconoutds(on) totalhconlcon p=idrk p=i(1d)rk p=pp ...(15) where the r ds(on) will increases as mosfet junc- tion temperature increases, k is r ds(on) temperature dependency. as a result, r ds(on) should be selected for the worst case. conduction loss should not exceed package rating or overall system thermal budget. switching loss is mainly caused by crossover conduction at the switching transition. the total switching loss can be approximated. swinoutsws 1 pvitf 2 = . ..(16) where i out is output current, t sw is the sum of t r and t f which can be found in mosfet datasheet, and f s is switching frequency. swithing loss p sw is fre- quency dependent. also mosfet gate driver loss should be consid- ered when choosing the proper power mosfet. mosfet gate driver loss is the loss generated by dis- charg i ng the gate capacitor and is dissipated in driver circuits.it is proportional to frequency and is defined as: gatehgatehgslgatelgss p(qvqv)f =+ ...(17) where q hgate is the high side mosfets gate charge,q lgate is the low side mosfets gate charge,v hgs is the high side gate source voltage, and v lgs is the low side gate source voltage. this power dissipation should not exceed maxi- mum power dissipation of the driver device. output voltage calculation output voltage is set by reference voltage and external voltage divider. the reference voltage is fixed
nx2139a 14 rev. 2.3 03/19/09 at 0.75v. the divider consists of two ratioed resistors so that the output voltage applied at the fb pin is 0.75v when the output voltage is at the desired value. the following equation applies to figure 11, which shows the relationship between out v , ref v and volt- age divider. vout vref fb r2 r1 figure 11 - voltage divider 2ref 1 out ref rv r= v-v ...(18) where r 2 is part of the compensator, and the value of r 1 value can be set by voltage divider. mode selection nx2139a can be operated in pfm mode, ultra- sonic pfm mode, ccm mode and shutdown mode by applying different voltage on ensw/mode pin. when vcc applied to ensw/mode pin, nx2139a is in pfm mode. the low side mosfet emu- lates the function of diode when discontinuous con- tinuous mode happens, often in light load condition. during that time, the inductor current crosses the zero ampere border and becomes negative current. when the inductor current reaches negative territory, the low side mosfet is turned off and it takes longer time for the output voltage to drop, the high side mosfet waits longer to be turned on. at the same time, no matter light load and heavy load, the on time of high side mosfet keeps the same. therefore the lightier load, the lower the switching frequency will be. in ultrosonic pfm mode, the lowest frequency is set to be 25khz to avoid audio frequency modulation. this kind of reduc- tion of frequency keeps the system running at light light with high efficiency. in ccm mode, inductor current zero-crossing sensing is disabled, low side mosfet keeps on even when inductor current becomes negative. in this way the efficiency is lower compared with pfm mode at light load, but frequency will be kept constant. over current protection over current protection for nx2139a is achieved by sensing current through the low side mosfet. an typical internal current source of 24ua flows through an external resistor connected from ocset pin to sw node sets the over current protection threshold. when synchronous fet is on, the voltage at node sw is given as swldson v=-ir the voltage at pin ocset is given as ocpocpsw ir+v when the voltage is below zero, the over current occurs as shown in figure below. ocp comparator ocp 24ua ocp i ocp r sw vbus figure 12 - over voltage protection the over current limit can be set by the following equation. = setocpocpdson iir/r if the low side mosfet r dson =10m w at the ocp occuring moment, and the current limit is set at 12a, then setdson ocp ocp ir 12a10m r5k i24ua w ===w choose r ocp =5k w
nx2139a 15 rev. 2.3 03/19/09 power good output power good output is open drain output, a pull up resistor is needed. typically when softstart is finised and fb pin voltage is over 90% of v ref , the pgood pin is pulled to high after a 1.6ms delay. smart over output voltage protection active loads in some applications can leak cur- rent from a higher voltage than v out , cause output volt- age to rise. when the fb pin voltage is sensed over 112% of v ref , the high side mosfet will be turned off and low side mosfet will be turned on to discharge the v out . nx2139a resumes its switching operation af- ter fb pin voltage drops to v ref . if fb pin voltage keeps rising and is sensed over 125% of v ref , the low side mosfet will be latched to be on to discharge the output voltage and over voltage protection is triggered. to resume the switching opera- tion, resetting voltage on pin vcc or pin en is neces- sary. under output voltage protection typically when the fb pin voltage is under 70% of v ref , the high side and low side mosfet will be turned off. to resume the switching operation, vcc or ensw has to be reset. ldo selection guide nx2139a offers a ldo controller. the selection of mosfet to meet ldo is more straight forward. the mosfet has to be logic level mosfet and its rdson at 4.5v should meet the dropout requirement. for example. v ldoin =1.8v v ldoout =1.5v i load =2a the maximum rdson of mosfet should be rdsonldoinldooutload r(vv)i (1.8v1.5v)/2a0.15 =- =-=w most of mosfets can meet the requirement. more important is that mosfet has to be selected right package to handle the thermal capability. for ldo, maximum power dissipation is given as lossldoinldooutload p(vv)i (1.8v1.5v)2a0.6w =- =-= select mosfet si4800 with 33m w r dson is sufficient. ldo compensation the diagram of ldo controller including vcc regulator is shown in the following figure. rf1 rf2 rc cc + ldo input rload esr co vref ldofb ldodrv rb cb figure 13 - nx2139a ldo controller. rb and cb have fixed value which is used to com- pensate the comparater of the ldo controller. set rb=50ohm, cb=33nf. for most low frequency capacitor such as elec- trolytic, poscap, oscon, etc, the compensation pa- rameter can be calculated as follows. m c of1m gesr 1 c= 2fr1+gesr p where f o is the desired crossover frequency. typically, when the poscap and electrical ca- pacitor is chosen as output capacitor, crossover fre- quency f o has to be 2 to 3 times higher than zero caused by esr. in this example, we select fo=150khz. g m is the forward trans-conductance of mosfet. for si4800, g m =19. select rf1=7.5kohm. output capacitor is sanyo poscap 4tpe150mi with 150uf, esr=18mohm. c 119s18m c= =36pf 2150khz7.5k1+19s18m w pww typically c c is chosen to be 1 to 1.5 times smaller than calculated value to compensate parasitic effect.
nx2139a 16 rev. 2.3 03/19/09 here c c is chosen to be 33pf. for electrolytic or poscap, r c is typically selected to be zero. r f2 is determined by the desired output voltage. f1ref f2 ldooutref rv r= vv 7.5k0.75v = 1.5v0.75v =7.5k - w - w choose r f2 =7.5k w. when ceramic capacitors or some low esr bulk capacitors are chosen as ldo output capacitors, the zero caused by output capacitor esr is so high that crossover frequency f o has to be chosen much higher than zero caused by r c and c c and much lower than zero caused by esr . for example, 10uf ceramic is used as output capacitor. we select fo=300khz, r f1 =7.5kohm and select mosfet si4800(g m =19). r c and c c can be calculated as follows. out m ooout cf1 out m m out v 1+g 2fci r=r v g g i 1.5v 1+19s 2300khz20uf 2a =7.5k 1.5v 19s 19s 2a =14.9k p p w w typically r c is chosen to be 1 to 1.5 times smaller than calculated value to compensate parasitic effect. choose r c =20k w. o c cm 10c c= rg 1020uf = 20k19s =0.53nf w choose c c =1000pf. current limit for ldo current limit of ldo is achieved by sensing the ldo feedback voltage. when ldo_fb pin is below 70% of v ref , the ic goes into latch mode. the ic will turn off all the channel until vcc or ensw resets. power good for ldo power good output is open drain output, a pull up resistor is needed. typically when softstart is finised and ldofb pin voltage is over 90% of v ref , the ldopgood pin is pulled to high. layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. there are two sets of components considered in the layout which are power components and small sig- nal components. power components usually consist of input capacitors, high-side mosfet, low-side mosfet, inductor and output capacitors. a noisy en- vironment is generated by the power components due to the switching power. small signal components are connected to sensitive pins or nodes. a multilayer lay- out which includes power plane, ground plane and sig- nal plane is recommended . layout guidelines: 1. first put all the power components in the top layer connected by wide, copper filled areas. the input capacitor, inductor, output capacitor and the mosfets should be close to each other as possible. this helps to reduce the emi radiated by the power loop due to the high switching currents through them. 2. low esr capacitor which can handle input rms ripple current and a high frequency decoupling ceramic cap which usually is 1uf need to be practi- cally touching the drain pin of the upper mosfet, a plane connection is a must. 3. the output capacitors should be placed as close as to the load as possible and plane connection is re- quired. 4. drain of the low-side mosfet and source of the high-side mosfet need to be connected thru a plane and as close as possible. a snubber needs to be placed as close to this junction as possible.
nx2139a 17 rev. 2.3 03/19/09 5. source of the lower mosfet needs to be con- nected to the gnd plane with multiple vias. one is not enough. this is very important. the same applies to the output capacitors and input capacitors. 6. hdrv and ldrv pins should be as close to mosfet gate as possible. the gate traces should be wide and short. a place for gate drv resistors is needed to fine tune noise if needed. 7. vcc capacitor, bst capacitor or any other by- passing capacitor needs to be placed first around the ic and as close as possible. the capacitor on comp to gnd or comp back to fb needs to be place as close to the pin as well as resistor divider. 8. the output sense line which is sensing output back to the resistor divider should not go through high frequency signals, should be kept away from the in- ductor and other noise sources. the resistor divider must be located as close as possible to the fb pin of the device. 9. all gnds need to go directly thru via to gnd plane. 10. in multilayer pcb, separate power ground and analog ground. these two grounds must be con- nected together on the pc board layout at a single point. the goal is to localize the high current path to a sepa- rate loop that does not interfere with the more sensi- tive analog control function.
nx2139a 18 rev. 2.3 03/19/09 demoboard schematic figure 14 - nx2139a schematic for the demoboard layout r7 1m vcc c7 10u ldoout r10 7.5k 5v vcc r6 10 c15 330p r4 2.2 u1 nx2139/mlpq-16/3x3 dh 12 bst 13 sw 11 dl 8 lin_drv 7 vout 1 fb 3 en 15 vcc 2 vccp 9 pgood 4 ocp 10 lin_fb 6 ton 16 gnd 17 lin_pgood 5 lin_en 14 r3 10k gnd r5 10.5k ldoin c3 10u cin2 4.7u/25v m3 si4800 1 4 8 5 6 7 2 3 co1 2r5tpe330mc c18 1n r17 20k bus 1 5v 1 c19 33n r18 50 r11 100k cin3 4.7u/25v c6 1n ldoout r15 2.2 c9 1.5n cin1 10u/25v r2 0 c2 1u vout lo do5010h-152 1 2 ldodrv ldoin out r19 7.5k c16 1u r20 7.5k c17 1u co2 4.7u/6.3v m1 irf7807 1 4 8 5 6 7 2 3 m2 ao4714 1 4 8 5 6 7 2 3 r8 100k bus
nx2139a 19 rev. 2.3 03/19/09 demoboard layout figure 15 top layer figure 16 ground layer
nx2139a 20 rev. 2.3 03/19/09 figure 18 bottom layer figure 17 power layer
nx2139a 21 rev. 2.3 03/19/09 mlpq 16 pin 3 x 3 package outline dimensions symbol name min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.600 1.750 0.063 0.069 e 2.950 3.050 0.116 0.120 e2 1.600 1.750 0.063 0.069 e l 0.325 0.450 0.013 0.018 m 0.203ref 0.50bsc 1.5ref dimensions in inches 0.008ref 0.50bsc 0.059ref dimensions in millimeters

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